The present invention relates to a semiconductor memory device, more particularly to a single-transistor single-capacitor dynamic random-access memory (DRAM) with bit lines split into a plurality of blocks and with an improved capacitance ratio between the capacitance of the memory cells to the bit line capacitance, wherein the number of blocks in which charging and discharging of the bit lines are performed is minimized and the maximum power consumption is reduced.
In general, in a DRAM using memory cells each composed of a single capacitor and a single transistor, the smaller the capacitance ratio of the capacitance of the bit lines with respect to the capacitance of the memory cells, the larger the change in the bit line potential upon reading of data and, thus, the more reliable the reading of memory data and the more dependable the memory device. However, in recent years, semiconductor memory devices have been made increasingly greater in density and the individual memory cells have become smaller in size, resulting in smaller capacitances of the memories. On the other hand, the number of memory cells connected to each bit line has increased and the bit lines have become longer in length, resulting in a greater increase in the capacitances of the bit lines. For this reason, the increase in memory capacities has led to a disadvantageously large ratio between the capacitance of the memory cells and the bit line capacitance and thus a reduction in dependability.
To prevent such problems, there has previously been proposed, in Japanese Kokai No. 59-101093 of the present assignee, a DRAM wherein bit lines are split into a plurality of blocks and the bit lines are sequentially driven by each block so as to reduce the bit line capacitance during readout and thereby ensure reliable reading of memory data. Such a DRAM having split blocks of bit lines is also disclosed in FIG. 7 of U.S. Pat. No. 4,122,546 of Paul-Werner von Basse, assigned to Siemens.
On the other hand, from the viewpoint of improving the mounting density, which is limited by heat radiation characteristics during mounting of the DRAM, and of reducing the capacitance of the power supply circuit, it is desirable to reduce the maximum power consumption of the DRAM as much as possible.
In a DRAM considered before the present invention, having such split blocks of bit lines as described above, the maximum power consumption is large, as is described below in more detail with reference to the attached drawings.